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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| 14_Verilog_Testbenches.pdf | 2021-04-16 21:45 | 554K | |
| EVITA_VERILOG.zip | 2019-06-14 13:52 | 4.2M | |
| Jezyk verilog w projektowaniu ukladow fpga.PDF | 2019-06-14 13:52 | 479K | |
| Kurs verilog.pdf | 2019-06-14 13:52 | 150K | |
| Verilog Tutorial.PDF | 2019-06-14 13:52 | 4.9M | |
| instrukcja_instalacji.pdf | 2021-04-18 22:27 | 33K | |
| instrukcja_lab.docx | 2021-06-28 17:32 | 208K | |
| instrukcja_lab.pdf | 2021-09-10 13:43 | 234K | |
| instrukcja_testbench.pdf | 2021-05-10 12:34 | 18K | |
| modelsim_tutorial_2011.pdf | 2019-06-14 13:52 | 1.5M | |